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1 of 22 rev: 070605 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . features 8051-compatible microprocessor adapts to its task ? accesses between 8kb and 64kb of nonvolatile sram ? in-system programming via on-chip serial port ? can modify its own program or data memory ? accesses memory on a separate byte-wide bus crash-proof operation ? maintains all nonvolatile resources for over 10 years ? power-fail reset ? early warning power-fail interrupt ? watchdog timer ? user-supplied lithium battery backs user sram for program/data storage software security ? executes encrypted programs to prevent observation ? security lock prevents download ? unlocking destroys contents fully 8051 compatible ? 128 bytes scratchpad ram ? two timer/counters ? on-chip serial port ? 32 parallel i/o port pins pin configuration ordering information part temp range max clock speed (mhz) pin- package ds5000fp-16 0c to +70c 16 80 qfp ds5000fp-16+ 0c to +70c 16 80 qfp + denotes a pb-free/rohs -compliant device. ds5000fp soft microprocessor chip www.maxim-ic.com this data sheet must be used in conjunction with the secure microcontroller user?s guide , which contains operating information. this data sheet provides ordering information, pinout, and electrica l specifications. download the secu re microcontroller user?s guide at www.maxim-ic.com/microcontrollers . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p0.4/ad4 n.c. n.c. ba9 p0.3/ad3 ba8 p0.2/ad2 ba13 p0.1/ad1 r/w p0.0/ad0 v cc0 v cc v cc p1.0 ba14 p1.1 ba12 p1.2 ba7 p1.3 n.c. n.c. ba6 p2.6/a14 n.c. n.c. bd3 p2.5/a13 bd2 p2.4/a12 bd1 p2.3/a11 bd0 v li gnd gnd p2.2/a10 p2.1/a9 p2.0/a8 xtal1 xtal2 p3.7/rd p3.6/wr p3.5/t1 n.c. n.c. p3.4/t0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 ba11 p1.4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p0.5/ad5 ba5 ce2 p1.5 p0.6/ad6 ba4 ba10 p1.6 p0.7/ad7 ba3 ce1 p1.7 ea n.c. n.c. ba2 bd7 rst a le ba1 bd6 p3.0/rxd psen ba0 bd5 p3.1/txd p2.7/a15 p3.2/int0 bd4 p3.3/int1 ds5000fp top view qfp
ds5000fp 2 of 22 description the ds5000fp soft microprocessor chip is an 8051-compatible processor based on nv ram technology. it is substantially more flexible than a standard 8051, yet provides full compatibility with the 8051 instruction set, timers, serial port, and parallel i/o ports. by using nv ram instead of rom, the user can program and then reprogram the microcontroller while in-system. the application software can even change its own operation, which allows frequent software upgrades, adaptive programs, customized systems, etc. in addition, by using nv sram, the ds 5000fp is ideal for data-logging applications and it connects easily to a dallas real-time clock for time stamp and date. the ds5000fp provides the benefits of nv ram without using i/o resources. it uses a nonmultiplexed byte-wide address and data bus for memory access. th is bus can perform all memory access and provides decoded chip enables for sram. this leaves the 32 i/o port pins free for app lication use. the ds5000fp uses ordinary sram and battery backs the memory cont ents with a user?s external lithium cell. data is maintained for over 10 years with a very sma ll lithium cell. a ds5000fp also provides crash-proof operation in portable systems or systems with unreliable power. these features include the ability to save the operating state, power-fail reset, power-fail interrupt, and watchdog timer. a user loads programs into the ds5000fp via its on-chip serial bootstrap loader. this function supervises the loading of code into nv ram, valid ates it, and then becomes transparent to the user. software can be stored in an 8-kbyte or 32-kbyte cmos sram. using its internal partitioning, the ds5000fp will divide this common ram into user programmable code and data segments. this partition can be selected at program loading time, but can be modified anytime later. it will decode memory access to the sram, communicate via its byte-wide bus and write-protect the memory portion designated as rom. combining program and data st orage in one device saves board space and cost. the ds5000fp can also access a second 32 kbytes of nv ram but this area is restricted to data memory. the ds2250(t) and ds5000(t) are available for a user who wants a pre-constructed module using the ds5000fp, ram, lithium cell, and opti onal real-time clock. each device is described in separate data sheets, available on our website at www.maxim-ic.co m/microcontrollers . more details are contained in the secure microcontroller user?s guide .
ds5000fp 3 of 22 ds5000fp block diagram figure 1
ds5000fp 4 of 22 pin description pin name function 15, 17, 19, 21, 25, 27, 29, 31 p1.0?p1.7 general-purpose i/o port 1 34 rst active-high reset input. a logic 1 applied to this pin activates a reset state. this pin is pulled down internally so this pin can be left unconnected if not used. 36 p3.0/ rxd general-purpose i/o port pin 3.0. also serves as the receive signal for the on board uart. this pin should not be connected directly to a pc com port. 38 p3.1/ txd general-purpose i/o port pin 3.1. also serves as the transmit signal for the on- board uart. this pin should not be connected directly to a pc com port. 39 p3.2/ int0 general-purpose i/o port pin 3.2. also serves as the active-low external interrupt 0. 40 p3.3/ int1 general-purpose i/o port pin 3.3. also serves as the active-low external interrupt 1. 41 p3.4/t0 general-purpose i/o port pin 3.4. also serves as the timer 0 input. 44 p3.5/t1 general-purpose i/o port pin 3.5. also serves as the timer 1 input. 45 p3.6/ wr general-purpose i/o port pin. also serves as the write strobe for expanded bus operation. 46 p3.7/ rd general-purpose i/o port pin. also serves as the read strobe for expanded bus operation. 47, 48 xtal2, xtal1 crystal connections. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 52, 53 gnd logic ground 49, 50, 51, 56, 58, 60, 64, 66 p2.0?p2.7 general-purpose i/o port 2. also serves as the msb of the expanded address bus. 68 psen program store enable. this active-low signal is used to enable an external program memory when using the expanded bus. it is normally an output and should be unconnected if not used. psen is also used to invoke the bootstrap loader. at this time, psen will be pulled down externally. this should only be done once the ds5000fp is already in a reset state. the device that pulls down should be open drain since it must not interfere with psen under normal operation. 70 ale address latch enable. used to de-multiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a ?373 type transparent latch. when using a parallel programmer, this pin also assumes the prog function for programming pulses. 73 ea external access. this pin forces the ds5000fp to behave like an 8031. no internal memory (or clock) will be available when this pin is at a logic low. since this pin is pulled down internally, it should be connected to +5v to use nv ram. in a parallel programmer, this pin also serves as v pp for super voltage pulses.
ds5000fp 5 of 22 pin description (continued) pin name function 11, 9, 7, 5, 1, 79, 77, 75 p0.0?p0.7 general-purpose i/o port 0. this port is open-drain and cannot drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 13, 14 v cc power supply, +5v 16, 8, 18, 80, 76, 4, 6, 20, 24, 26, 28, 30, 33, 35, 37 ba14? ba0 byte-wide address bus bits 14?0. this 15-bit bus is combined with the nonmultiplexed data bus (bd7?bd0) to access nv sram. decoding is performed on ce1 and ce2 . read/write access is controlled by r/ w. ba14?ba0 connect directly to an 8k or 32k sram. if an 8k ram is used, ba13 and ba14 are unconnected. note: ba13 and ba14 are inverted from the true logical address. ba14 is lithium backed. 71, 69, 67, 65, 61, 59, 57, 55 bd7?bd0 byte-wide data bus bits 7?0. this 8-bit bidirectional bus is combined with the nonmultiplexed address bus (ba14?ba0) to access nv sram. decoding is performed on ce1 and ce2 . read/write access is controlled by r/ w . bd7?bd0 connect directly to an 8k or 32k sram, and optionally to a real-time clock. 10 r/ w read/write (active low). this signal provides the write enable to the srams on the byte-wide bus. it is controlled by the memory map and partition. the blocks selected as program (rom) is write protected. 74 ce1 active-low chip enable 1. this is the primary decoded chip enable for memory access on the byte-wide bus. it connects to the chip enable input of one sram. ce1 is lithium backed. it will remain in a logic high inactive state when v cc falls below v li . 78 ce2 active-low chip enable 2. this chip enable is provided to bank switch to a second block of 32k bytes of nonvolatile data memory. it connects to the chip enable input of one sram or one lithium-backed peripheral such a real-time clock. ce2 is lithium backed. it will remain in a logic high inactive state when v cc falls below v li . 12 v cco v cc output. this is switched between v cc and v li by internal circuits based on the level of v cc . when power is above the lithium input, power will be drawn from v cc . the lithium cell remains isolated from a load. when v cc is below v li , the v cco switches to the v li source. v cco is connected to the v cc pin of an sram. 54 v li lithium voltage input. connect to a lithium cell greater than v limin and no greater than v limax as shown in the electrical specifications. nominal value is +3v. 2, 3, 22, 23, 32, 42, 43, 62, 63, 72 n.c. no connection. do not connect.
ds5000fp 6 of 22 instruction set the ds5000fp executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. as a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the ds 5000fp. a complete descrip tion of the instruction set and operation are provided in the secure microcontroller user?s guide . also note that the ds5000fp is embodied in the ds5000(t) and ds2250(t) modules. the ds5000(t) combines the ds5000fp with one sram of either 8 or 32 kbytes and a lithium cell. an optional real time clock is also available in the ds5000t. this is packaged in a 40-pin dip module. the ds2250(t) is an identical function in a simm form factor. it also offers the option of a second 32k sram mapped as data on chip enable 2. memory organization figure 2 illustrates the memory map accessed by the ds5000fp. the entire 64k of program and 64k of data is available. the ds5000fp ma ps 32k of this space into the sram connected to the byte-wide bus. this is the area from 0000h to 7fffh (32k) and is reached via ce1 . any area not mapped into the nv ram is reached via the expanded bus on ports 0 & 2. selecting ce2 provides another 32k of potential data storage. when ce2 is used, no data is available on the ports. the memory map is covered in detail in the secure microcontroller user?s guide . figure 3 illustrates a typical memory connection for a system using 8k bytes of sram. figure 4 shows a similar system with 32 kbytes. the byte-wide addre ss bus connects to the sram address lines. the bi- directional byte-wide data bus connects the data i/o lines of the sram. ce1 provides the chip enable and r/ w is the write enable. an additi onal ram could be connected to ce2 , with common connections for r/ w , ba14-0, and bd7-0.
ds5000fp 7 of 22 power management the ds5000fp monitors power to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. it uses the lithium cell at v li as a reference in determining the switch points. these are called v pfw , v ccmin , and v li respectively. when v cc drops below v pfw , the ds5000fp will perform an interrupt vector to location 2bh if the power-fail warning was enabled. full processor operation continues regardless. wh en power falls further to v ccmin , the ds5000fp invokes a reset state. no further code execution will be performed unless power rises back above v ccmin . ce1 , ce2 , r/ w go to an inactive (logic 1) state. any address lines that are high (due to encryption) will follow v cc , except for ba14, which is lithium backed. v cc is still the power source at this time. when v cc drops further to below v li , internal circuitry will switch to the lithium cell fo r power. the majority of internal circuits will be disabled and the remaining nonvola tile states will be retained. the lithium cell will power any devices connected to vcco at this time. v cco will be at the lithium battery vo ltage less a diode drop. this drop will vary depending on the load. low-leakage srams s hould be used for this reason. when a module is used, the lithium cell is selected by dallas so absolute specifications are provided for the switch thresholds. when using the ds5000fp, the user must select the appropriate battery. the following formulas apply to the switch function: v pfw = 1.45 x v li v ccmin = 1.40 x v li v li switch = 1.0 x v li memory map of the ds5000fp figure 2
ds5000fp 8 of 22 ds5000fp connection to 8k x 8 sram figure 3 ds5000fp connection to 32k x 8 sram figure 4
ds5000fp 9 of 22 absolute maximum ratings voltage range on any pin relative to ground??????????????...???-0.3v to + (v cc + 0.5v) voltage range on v cc relative to ground????????.???.????????..???-0.3v to +7.0v operating temperature range?????????????.?.????????????..?..0c to +70c storage temperature range??????????????...????????????..?..-40c to +70c soldering temperature range?????????????????..see ipc/jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. dc characteristics (v cc = 5v 5%, t a = 0 c to +70 c.) parameter symbol min typ max units notes input low voltage v il -0.3 0.8 v 1 input high voltage v ih1 2.0 v cc +0.3 v 1 input high voltage rst, xtal1 v ih2 3.5 v cc + 0.3 v 1 output low voltage at i ol = 1.6ma (ports 1, 2, 3) v ol1 0.15 0.45 v output low voltage at i ol = 3.2ma (ports 0, ale, psen , ba14?ba0, bd7?bd0, r/ w , ce 1-2) v ol2 0.15 0.45 v 1 output high voltage at i oh = -80 a (ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage at i oh = -400 a (ports 0, ale, psen , ba14?ba0, bd7?bd0, r/ w , ce 1-2) v oh2 2.4 4.8 v 1 input low current v in = 0.45v (ports 1, 2, 3) i il -50 a transition current; 1 to 0 v in = 2.0v (ports 1, 2, 3) i tl -500 a input leakage current 0.45 < v in < v cc (port 0) i l 10 a rst, ea pulldown resistor r re 40 125 k stop mode current i sm 80 a 4 power-fail warning voltage v pfw 4.15 4.6 4.75 v 1, 6 minimum operating voltage v ccmin 4.05 4.5 4.65 v 1, 6 operating voltage v cc v cc(min) 5.5 v 1, 6 lithium supply voltage v li 2.9 3.3 v 1 programming supply voltage (parallel program mode) v pp 12.5 13 v 1 program supply current i pp 15 20 ma
ds5000fp 10 of 22 dc characteristics (continued) (v cc = 5v 5%, t a = 0c to +70c.) parameter symbol min typ max units notes operating current at 16mhz i cc 36 ma 2 idle mode current at 12mhz i idle 6.2 ma 3 output supply voltage v cco1 v cc - 0.3 v 1 output supply voltage (battery-backed mode) v cco2 v li - 0.65 v li - 0.5 v 8 output supply current at v cco = v cc - 0.3v i cco1 80 ma 2 battery-backed quiescent current i li 5 75 na 7 notes: 1. all voltages are referenced to ground. 2. maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10ns, v il = 0.5v; xtal2 disconnected; ea = rst = port0 = v cc . 3. idle mode i cc is measured with all output pins disc onnected; xtal1 driven at 12mhz with t clkr , t clkf = 10ns, v il = 0.5v; xtal2 disconnected; ea = port0 = v cc , rst = v ss . 4. stop mode i cc is measured with all output pins disconnected; ea = port0 = v cc ; xtal2 not connected; rst = v ss . 5. crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit un til the first clock pulse is produced by the on-chip oscillator. the user should check with the crys tal vendor for the worst-case spec on this time. 6. assumes v li = 3.3v maximum. 7. i li is the current drawn from v li when v cc = 0v and v cco is disconnected. 8. i cco = 10 a.
ds5000fp 11 of 22 ac characteristics: expanded bus mode timing specifications (v cc = 5v 5%, t a = 0 c to +70 c.) # parameter symbol min max units 1 oscillator frequency 1/t clk 1.0 16 mhz 2 ale pulse width t alpw 2t clk -40 ns 3 address valid to ale low t avall t clk -40 ns 4 address hold after ale low t avaav t clk -35 ns at 12mhz 4t clk -150 5 ale low to valid instruction in at 16mhz t allvi 4t clk -90 ns 6 ale low to psen low t allpsl t clk -25 ns 7 psen pulse width t pspw 3t clk -35 ns at 12mhz 3t clk -150 8 psen low to valid instruction in at 16mhz t pslvi 3t clk -90 ns 9 input instruction hold after psen going high t psiv 0 ns 10 input instruction float after psen going high t psix t clk -20 ns 11 address hold after psen going high t psav t clk -8 ns at 12mhz 5t clk -150 12 address valid to valid instruction in at 16mhz t avvi 5t clk -90 ns 13 psen low to address float t pslaz 0 ns 14 rd pulse width t rdpw 6t clk -100 ns 15 wr pulse width t wrpw 6t clk -100 ns at 12mhz 5t clk -165 16 rd low to valid data in at 16mhz t rdldv 5t clk -105 ns 17 data hold after rd high t rdhdv 0 ns 18 data float after rd high t rdhdz 2t clk -70 ns at 12mhz 8 clk -150 19 ale low to valid data in at 16mhz t allvd 8t clk -90 ns at 12mhz 9t clk -165 20 valid address to valid data in at 16mhz t avdv 9t clk -105 ns 21 ale low to rd or wr low t allrdl 3t clk -50 3t clk +50 ns 22 address valid to rd or wr low t avrdl 4t clk -130 ns 23 data valid to wr going low t dvwrl t clk -60 ns at 12mhz 7t clk -150 24 data valid to wr high at 16mhz t dvwrh 7t clk -90 ns 25 data valid after wr high t wrhdv t clk -50 ns 26 rd low to address float t rdlaz 0 ns 27 rd or wr high to ale high t rdhalh t clk -40 t clk +50 ns
ds5000fp 12 of 22 expanded program memory read cycle expanded data memory read cycle
ds5000fp 13 of 22 expanded data memory write cycle external clock timing
ds5000fp 14 of 22 ac characteristics: external clock drive (v cc = 5v 5%, t a = 0 c to +70 c.) # parameter symbol min max units at 12mhz 20 28 external clock high time at 16mhz t clkhpw 15 ns at 12mhz 20 29 external clock low time at 16mhz t clklpw 15 ns at 12mhz 20 30 external clock rise time at 16mhz t clkr 15 ns at 12mhz 20 31 external clock fall time at 16mhz t clkf 15 ns ac characteristics: serial port timing?mode 0 (v cc = 5v 5%, t a = 0 c to +70 c.) # parameter symbol min max units 35 serial port cycle time t spclk 12t clk s 36 output data setup to rising clock edge t doch 10t clk -133 ns 37 output data hold after rising clock edge t chdo 2t clk -117 ns 38 clock rising edge to input data valid t chdv 10t clk -133 ns 39 input data hold after rising clock edge t chdiv 0 ns serial port timing?mode 0
ds5000fp 15 of 22 ac characteristics: power cycle timing (v cc = 5v 5%, t a = 0 c to +70 c.) # parameter symbol min max units 32 slew rate from v ccmin to v limax t f 40 s 33 crystal startup time t csu (note 5) 34 power-on reset delay t por 21,504 t clk power cycle timing
ds5000fp 16 of 22 ac characteristics: parallel program load timing (v cc = 5v 5%, t a = 0 c to +70 c.) # parameter symbol min max units 40 oscillator frequency 1/t clk 1.0 12.0 mhz 41 address setup to prog low t avprl 0 42 address hold after prog high t prhav 0 43 data setup to prog low t dvprl 0 44 data hold after prog high t prhdv 0 45 p2.7, 2.6, 2.5 setup to v pp t p27hvp 0 46 v pp setup to prog low t vphprl 0 47 v pp hold after prog low t prhvpl 0 48 prog width low t prw 2400 t clk 49 data output from address valid t avdv 48 (1800*) t clk 50 data output from p2.7 low t dvp27l 48 (1800*) t clk 51 data float after p2.7 high t p27hdz 0 48 (1800*) t clk 52 delay to reset/ psen active after power-on t porpv 21,504 t clk 53 reset/ psen active (or verify inactive) to v pp high t ravph 1200 t clk 54 v pp inactive (between program cycles) t vpppc 1200 t clk 55 verify active time t vft 48 (2400*) t clk * second set of numbers refers to expanded memory programming up to 32kbytes.
ds5000fp 17 of 22 parallel program load timing capacitance (t a = +25 c, test frequency = 1mhz.) parameter symbol min typ max units notes output capacitance c o 10 pf input capacitance c i 10 pf
ds5000fp 18 of 22 ac characteristics: byte-wide address/data bus timing (v cc = 5v 5%, t a = 0 c to +70 c.) # parameter symbol min max units 56 delay to embedded address valid from ce1 low during opcode fetch t ce1lpa 20 ns 57 ce1 or ce2 pulse width t cepw 4t clk -15 ns 58 embedded address hold after ce1 high during opcode fetch t ce1hpa 2t clk -20 ns 59 embedded data setup to ce1 high during opcode fetch t ovce1h 1t clk +40 ns 60 embedded data hold after ce1 high during opcode fetch t ce1hov 10 ns 61 embedded address hold after ce1 or ce2 high during movx t cehda 4t clk -30 ns 62 delay from embedded address valid to ce1 or ce2 low during movx t celda 4t clk -25 ns 63 embedded data hold setup to ce1 or ce2 high during movx (read) t daceh 1t clk +40 ns 64 embedded data hold after ce1 or ce2 high during movx (read) t cehdv 10 ns 65 embedded address valid to r/ w active during movx (write) t avrwl 3t clk -35 ns 66 delay from r/ w low to valid data out during movx (write) t rwldv 20 ns 67 valid data out hold time from ce1 or ce2 high t cehdv 1t clk -15 ns 68 valid data out hold time from r/ w high t rwhdv 0 ns 69 write pulse width (r/ w low time) t rwlpw 6t clk -20 ns
ds5000fp 19 of 22 byte-wide address/data bus opcode fetch cycle byte-wide address/data bus opcode fetch with data memory read
ds5000fp 20 of 22 byte-wide address/data bus opcode fetch with data memory write
ds5000fp 21 of 22 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) 56-g4005-001 millimeters dim min max a - 3.15 a1 0.25 - a2 2.55 2.87 b 0.30 0.50 c 0.13 0.23 d 23.70 24.10 d1 19.90 20.10 e 17.40 18.10 e1 13.90 14.10 e 0.80 bsc l 0.65 0.95
ds5000fp 22 of 22 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. revision history date description 070605 1) added pb-free part to ordering information table. 2) added operating voltage specification. (t his is not a new specification because operating voltage is implied in the tes ting limits, but rather a clarification.) 3) updated absolute maximum ratings soldering temperature to reference jedec standard. 4) added voltage rang on v cc relative to ground specifica tion to absolute maximums. 5) changed ?secure microcontroller data b ook? references to ?secure microcontroller user?s guide.?

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